Contoh Program D Flip-Flop Pada VHDL

Sebuah contoh program vhdl dari D flip-flop edge triggered positif dengan asynchronous Reset:

 
library ieee;

use ieee.std_logic_1164.all;

entity DFF_RST is

       port (CLK, RESET, D : in std_logic;

                 Q : out std_logic);

end DFF_RST;

architecture BEHAV_DFF of DFF_RST is

 begin

   DFF_PROCESS: process (CLK, RESET)

     begin

        if (RESET = ‘1’) then

        Q <= ‘0’;

        elsif (CLK’event and CLK = ‘1’) then

        Q <= D;

     end if;

  end process;

end BEHAV_DFF;